Image display apparatus

ABSTRACT

To provide an image display apparatus in which, even if pixel data is phase-expanded, the influence of differences in circuit characteristic can be dispersed between frames. The apparatus has a phase expansion circuit 380 to which are input a first video signal A1 having pixel data for driving pixels with positive voltages and a second video signal A2 having pixel data for driving pixels with negative voltages. The phase expansion circuit 380 forms six phase-expanded signals V1 to V6 from the first and second video signals A1 and A2. The phase-expanded signals are expanded into pixel data by extending the data length of items of the pixel data corresponding to some of the pixels periodically selected. The phase expansion circuit 380 outputs the phase-expanded signals to phase-expanded signal output lines in parallel with each other. The apparatus also has a connection change circuit 390 for changing connections between six phase-expanded signal output lines 388a to 388f and six signal supply lines 132a to 132f. Change of the order of expansion into six phase-expanded signals V1 to V6 by the phase expansion means and change of the combination of connections changed by the connection change circuit 390 while being linked to the expansion order are controlled by a timing generation circuit block 200. This timing generation circuit block 220 performs change control so that a expansion order first set with respect to the preceding frame is changed to a different expansion order in synchronization with vertical synchronization.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to an image display apparatus using aliquid crystal panel or the like and, more particularly, to an imagedisplay apparatus capable of reducing deterioration in image quality dueto a non-uniformity of elements while using phase-expanded pixelsignals. The present invention also relates to an image displayapparatus in which, if an input signal is a digital signal, polarityinversion and phase expansion of the digital signal are executed anddigital-to-analog conversion or the like is performed at a low rate.Further, the present invention relates to an image display apparatuswhich is capable of executing phase expansion a certain number of timesat the stages a digital signal and analog signal processed after thedigital signal.

2. Description of Related Art

An image display apparatus is known which uses a liquid crystal displaypanel in which a data-side drive circuit and a scanning-side drivecircuit are constituted of thin film transistors (TFTs). In this imagedisplay apparatus, matching is necessary between a frequency of a videosignal and an operating speed when the video signal is sampled.

Then, a process is conceivable in which pixel signals contained asserial data in the video signal are phase-expanded and a display is madeby using the phase-expanded pixel signals. That is, as shown in FIGS.22A and 22B, a phase expansion circuit 30 for expanding a video signalVIDEO in six phases is provided in a block 10 of a pixel displayapparatus. Panel drive video signals V(i) (i=1 to 6) in these phases arerespectively output from six output terminals OUT1 to OUT6 in accordancewith a control signal from a timing circuit block 20. Panel drive videosignals V(i) are supplied to groups of data signal lines 112 of a liquidcrystal panel 110 each corresponding to a row of six pixels in thehorizontal direction via sampling switches 134 connected to signalsupply lines 132. Panel drive video signals V(i) are video signalsexpanded in six phases from input video signal VIDEO by the phaseexpansion circuit 30. Therefore, each panel drive video signal V(i)contains pixel signals for every sixth pixel, and the frequency of thepanel drive video signal V(i) is lower than the frequency of input videosignal VIDEO. As a result, even if the operating speeds of the data-sidedrive circuit 130 and the scanning-side drive circuit 120, constitutedof thin film transistors, are low, the data-side drive circuit 130 canreliably sample, with the sampling switches 134, pixel signal PDcorresponding to each data signal line 112 from panel drive videosignals V(1) to V(6) supplied to terminals VIN1 to VIN6 in accordancewith sampling signals supplied from a shift register 136 for driving thesampling switches 134.

There is also a need to drive the liquid crystal panel by an alternatingcurrent signal. Therefore, the polarity of the liquid crystal drivevideo signal is always changed. Polarity inverting drive per dot is moreeffective in improving and stabilizing image qualities than polarityinverting drive per frame or polarity inverting drive per line.

Then, according to conventional art, as shown in FIG. 23, a polarityinversion circuit 40 is formed in a stage before the phase expansioncircuit 30. In the polarity inversion circuit 40, a signal outputcircuit 42 forms two video signals inverse in polarity from the inputvideo signal VIDEO and outputs these signals, and selectors 44a and 44b,formed of analog switches, change the polarity of the video signalsupplied to each of the sample and hold circuits of the phase expansioncircuit 30.

In the conventional image display apparatus, however, the phaseexpansion circuit 30 is provided with the circuits corresponding to thephases and these circuits may have different gains or offsets due tovariations in their characteristics, changes with time of theircomponent parts, or their mounted conditions, even though they have thesame circuit configuration. Therefore, even if input video signal VIDEOhas pixel signals PD uniform in brightness, there is a possibility ofthe pixel signals PD having different intensities with respect to thephases after phase expansion. The problem in such a case is that some ofthe pixels which are to be equal in brightness on the liquid crystalpanel 110 will be displayed with different degrees of brightness. Thatis, if panel drive video signal V(i) having an abnormal intensity issupplied to some data signal line 112 in each group of six data signallines 112, the corresponding difference in brightness appears as avertical line on the liquid crystal panel 110.

Moreover, in the conventional image display apparatus, the selectors 44aand 44b handle video signals at high frequencies. However, the frequencyof a video signal may be so high that they hardly follow up the signal.Therefore, when a display is made by using phase-expanded video signals,adaptation to video signals having certain high frequencies isimpossible particularly if the display is a one-dot polarity invertingdisplay.

SUMMARY OF THE INVENTION

The present invention has been developed to solve the above-describedproblems, and an object of the present invention is to provide a videodisplay apparatus which is adapted to the input of a high-frequencyimage by phase expansion, and which is arranged so that, even ifvariations in gain or offsets occur in circuits due to variations incharacteristics or changes with time of component parts, or mountedconditions of the circuits while the circuits have the sameconfiguration, the influence of variations in characteristics of thecircuits on the displayed picture with respect to phases can be reduced.

Another object of the present invention is to provide a video displayapparatus which is capable of performing signal processing without usinga circuit adapted to high frequencies, even if an image having a highfrequency is input, while still maintaining a small size and low price.

Still another object of the present invention is to provide a videodisplay apparatus which is capable of performing polarity inversion andphase expansion of a digital signal as well as digital-to-analogconversion at a low rate if a digital signal is input.

According to one aspect of the present invention, there is provided animage display apparatus having:

an image display unit in which pixels electrically connected to aplurality of data signal lines and to a plurality of scanning signallines are arrayed in a matrix form; and

scanning signal line selection means for supplying the scanning signallines with scanning signals for successively selecting the scanningsignal lines,

the apparatus driving the pixels by applying voltages to the pixels inaccordance with the data signals and the scanning signals whileinverting the polarities of the voltages applied to the pixels, theapparatus comprising:

phase expansion means supplied with a first video signal having serialpixel data for driving the pixels by voltages having a first polarity,and with a second video signal having serial pixel data for driving thepixels by voltages having a second polarity, the phase expansion meansforming, from the first and second video signals, m (where m is aninteger equal to or larger than 2) phase-expanded signals expanded intopixel data by extending the data length of items of the pixel datacorresponding to some of the pixels periodically selected, the phaseexpansion means outputting the phase-expanded signals to phase-expandedsignal output lines in parallel with each other;

signal supply means for supplying the pixel data to the plurality ofdata lines on the basis of the m phase-expanded signals input via msignal supply lines;

connection change means for changing connections between the mphase-expanded signal output lines and the m signal supply lines; and

change control means for controlling change of the order of expansioninto the m phase-expanded signals performed by the phase expansionmeans, and a combination of connections changed by the connection changemeans by linking the combination to the expansion order,

wherein the change control means performs change control so that anexpansion order first set with respect to the preceding frame is changedto a different expansion order in synchronization with verticalsynchronization.

According to the present invention, the order of phase expansion by thephase expansion means is changed and, as compensation for a change inthe sequence of serial pixel data thereby caused, a connection change ismade by the connection change means, thereby enabling the serial pixeldata to be always supplied to the predetermined pixels to display theimage. At this time, the phase expansion means changes the expansionorder first set with respect to the preceding frame to a differentexpansion order in synchronization with vertical synchronization, sothat the positions of deterioration in image quality due to acharacteristic difference between circuits are dispersed in one frameand are also dispersed with respect to another frame. Therefore, theproblem of a characteristic difference between circuits or the like asseen with the eye is thereby made negligible, thus achieving animprovement in image quality. Moreover, a characteristic margin ofcircuit components is increased to enable the image display apparatus tobe manufactured at a low cost.

According to the present invention, two video signals previously fixedin polarity may be input, and it is not always necessary to changesignals having first and second polarities with analog switches or thelike. Therefore, the present invention is also suitable for processingof a high-frequency image.

The above-described change control means may control change of theexpansion order between at least m expansion orders in accordance with apredetermined sequence and in synchronization with horizontalsynchronization.

Thus, the order of phase expansion in one frame is changed in accordancewith a predetermined sequence and in synchronization with horizontalsynchronization to disperse the influence of a difference incharacteristic between circuits. Also, change of the expansion order andchange of connections necessarily changed with the expansion order caneasily be controlled in accordance with the sequence.

The above-described change control means may form the m expansionsignals by alternately expanding the pixel data of the first and secondvideo signals.

If this is done, the polarities of the first and second video signalsare made opposite from each other, thereby facilitating realization of adot inverting drive.

The above-described phase expansion means may have m sample and holdsections connected to the m phase-expanded signal output lines, thefirst video signal being constantly input to one of two groups of thesample and hold sections, the second video signal being constantly inputto the other group of the sample and hold sections.

The first and second video signals are thereby input constantly to theparticular sample and hold circuits, so that the apparatus can beadapted for high-frequency images without requiring selectors or analogswitches in a stage before the phase expansion means.

According to another aspect of the present invention, there is providedan image display apparatus having:

an image display unit in which pixels electrically connected to aplurality of data signal lines and to a plurality of scanning signallines are arrayed in a matrix form;

scanning signal line selection means for supplying the scanning signallines with scanning signals for successively selecting the scanningsignal lines; and

signal supply means for supplying pixel data signals to the plurality ofdata signal lines,

the apparatus driving the pixels by applying voltages to the pixels inaccordance with the data signals and the scanning signals whileinverting the polarities of the voltages applied to the pixels, theapparatus comprising:

first phase expansion means supplied with a digital signal having pixeldata of a first data length corresponding to the position of each of thepixels, the first phase expansion means outputting two phase-expandeddigital signals in which items of the pixel data corresponding to someof the pixels periodically selected are expanded into pixel data havinga data length n (where n is an integer equal to or larger than 2) timeslonger than the first data length;

first and second branching means respectively supplied with thephase-expanded digital signals, each of the first and second branchingmeans branching a route for the phase-expanded digital signal into afirst route on which the polarity of the digital signal is not invertedand a second route on which the polarity of the digital signal isinverted by polarity inversion means;

first selection means for selecting one of the first and second routesbranched by the first branching means;

second selection means for selecting one of the first and second routesbranched by the second branching means; and

first and second digital-to-analog conversion means for respectivelyanalog-to-digital converting the two phase-expanded digital signalsselected by the first and second selection means to output two firstphase-expanded analog signals,

wherein the signal supply means supplies the pixel data signals to thedata signal lines on the basis of the two first phase-expanded analogsignals.

According to this invention, the pixel data of the digital signal isphase-expanded and the frequency of the digital signal is therebyreduced, so that the sampling frequency of the subsequent first andsecond digital-to-analog conversion means can be reduced to enableadaptation for high-frequency images. Also, the two phase-expandeddigital signals are branched into four to form signals having differentpolarities, and two of these signals are selected, thus enablinguniversal use for various polarity inverting drives.

According to still another aspect of the present invention, there isprovided an image display apparatus having:

an image display unit in which pixels electrically connected to aplurality of data signal lines and to a plurality of scanning signallines are arrayed in a matrix form;

scanning signal line selection means for supplying the scanning signallines with scanning signals for successively selecting the scanningsignal lines; and

signal supply means for supplying pixel data signals to the plurality ofdata signal lines,

the apparatus driving the pixels by applying voltages to the pixels inaccordance with the data signals and the scanning signals whileinverting the polarities of the voltages applied to the pixels, theapparatus comprising:

first phase expansion means supplied with a digital signal having pixeldata of a first data length corresponding to the position of each of thepixels, the first phase expansion means outputting two phase-expandeddigital signals in which items of the pixel data corresponding to someof the pixels periodically selected are expanded into pixel data havinga data length n (where n is an integer equal to or larger than 2) timeslonger than the first data length;

polarity determination means supplied with the two phase-expandeddigital signals, the polarity determination means determining thepolarities of the two phase-expanded digital signals by leading one ofthe phase-expanded digital signals to a first route on which thepolarity of the digital signal is not inverted and leading the other ofthe phase-expanded digital signals to a second route on which thepolarity of the digital signal is inverted by polarity inversion means;

first and second digital-to-analog conversion means for respectivelyanalog-to-digital converting the two phase-expanded digital signalshaving the determined polarities to output two first phase-expandedanalog signals,

wherein the signal supply means supplies the pixel data signals to thedata signal lines on the basis of the two first phase-expanded analogsignals.

According to this invention, the polarities of the two phase-expandeddigital signals are determined by a polarity determination circuit.Then, polarity inverting drive in the frame cycle only becomesimpossible and the number of kinds of usable polarity inverting drive isreduced. However, frequently demanded dot inverting and line invertingcan be performed and the number of circuits is markedly reduced.

The apparatus may further comprise second phase expansion means forforming, from the two first phase-expanded analog signals, n X N (whereN is an integer) second phase-expanded analog signals expanded intopixel data by extending the data length of items of the pixel datacorresponding to some of the pixels periodically selected, the secondphase expansion means outputting the second phase-expanded analogsignals to n X N phase-expanded signal output lines in parallel witheach other. In this case, the signal supply means supplies the pixeldata signals to the data signal lines on the basis of the n X N secondphase-expanded analog signals.

In this manner, phase expansion of the desired number of phases isexecuted by being separately performed two times as the first phaseexpansion of the digital signal and the second phase expansion of theanalog signals. Since the frequency of the digital signal is reduced bythe first phase expansion, the frequency of a clock fordigital-to-analog conversion and so on necessary before the second phaseexpansion can be reduced to enable adaptation for high-frequency images.

The above-described signal supply means may supply the pixel data to theplurality of data signal lines on the basis of the n X N secondphase-expanded analog signals input through n X N signal supply lines.

In this case, preferably, the apparatus further comprises connectionchange means for changing connections between the n X N phase-expandedsignal output line and the n X N signal supply lines; and

change control means for controlling change of the order of phaseexpansion performed by each of the first and second phase expansionmeans, and a combination of connections changed by the connection changemeans by linking the combination to the phase expansion order.

According to this arrangement, the order of phase expansion by the phaseexpansion means is changed and, as compensation for a change in thesequence of serial pixel data thereby caused, a connection change ismade by the connection change means, thereby enabling the serial pixeldata to be always supplied to the predetermined pixels to display theimage. Also, by changing the expansion order of the first and secondphase expansions, the influence of different circuit characteristics onimage qualities can be reduced.

A first-polarity gamma correction circuit and a first-polarity clampcircuit may be connected in a stage subsequent to the firstdigital-to-analog conversion means, and a second-polarity gammacorrection circuit and a second-polarity clamp circuit may be connectedin a stage subsequent to the second digital-to-analog conversion means.

In this case, a gamma correction circuit and a clamp circuit having oneof the first and second polarities may suffice for one signal line,thereby reducing the number of circuits.

The above-described change control means may control the first andsecond phase expansion means and the connection change means byselecting at least one of predetermined n X N phase expansion orders forthe first and second phase expansion means, and by also selecting one ofa plurality of predetermined combinations of connections as thecombination of connections changed by the connection change means.

The contents of the control performed by change controls means aresimplified thereby.

The above-described change control means may control change of the orderof phase expansion performed by the first and second phase expansionmeans and the combination of connections changed by the connectionchange means so that the voltages applied to the pixels differ inpolarity one from another with respect to the pixels connected in commonto each of the scanning signal lines.

A dot inverting drive on each scanning line is thereby enabled.

The above-described change control means may control change of the orderof phase expansion performed by the first and second phase expansionmeans and the combination of connections changed by the connectionchange means so that the voltages applied to the pixels are changed inpolarity one from another in synchronization with a horizontalsynchronization signal with respect to the pixels connected in common toeach of the data lines.

A line inverting drive on each data line is thereby enabled.

The above-described change control means may control change of the orderof phase expansion performed by the first and second phase expansionmeans and the combination of connections changed by the connectionchange means so that the data sampling section in which data of theleading pixel of one frame is sampled is changed with respect to framesin synchronization with a vertical synchronization signal.

In this manner, bad influences of circuit characteristics can also bedispersed between frames.

The present invention can suitably applied to image display apparatuses,such as a liquid crystal panel and a liquid crystal projector, for whicha polarity inversion drive is indispensable considering the life of theliquid crystal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an example of an image displayapparatus to which the present invention is applied.

FIG. 2 is a block diagram showing details of a data processing circuitblock of the image display apparatus shown in FIG. 1.

FIGS. 3A and 3B are circuit diagrams showing examples of first andsecond latch circuits shown in FIG. 2.

FIG. 4 is a timing chart for explanation of the data expansion operationof first and second phase expansion circuits shown in FIG. 2.

FIG. 5 is a schematic explanatory diagrams for explanation of kinds ofsampling signals input to the second phase expansion signal shown inFIG. 2 and line connection states correspondingly changed by aconnection change circuit.

FIG. 6 is a block diagram showing a portion of a timing generationcircuit block shown in FIG. 2.

FIG. 7 is a schematic explanatory diagram in which outputs of sample andhold circuits shown in FIG. 2 at the time of dot inverting drive arerearranged at pixel positions.

FIG. 8 is a schematic explanatory diagram in which outputs of the sampleand hold circuits shown in FIG. 2 at the time of line inverting driveare rearranged at pixel positions.

FIG. 9 is a schematic explanatory diagram in which outputs of the sampleand hold circuits shown in FIG. 2 at the time of frame inverting driveare rearranged at pixel positions.

FIG. 10 is a schematic explanatory diagram in which outputs of thesample and hold circuits shown in FIG. 2 when phase expansion areperformed by the sample and hold circuits so that the pixel data withthe leading addresses differ from each other between frames arerearranged at pixel positions.

FIG. 11 is a schematic explanatory diagram showing polarities of pixeldata at the time of dot inverting drive achieved by the drive shown inFIG. 7 or 10.

FIG. 12 is a schematic explanatory diagram showing polarities of pixeldata at the time of line inverting drive achieved by the drive shown inFIG. 8.

FIG. 13 is a schematic explanatory diagram showing polarities of pixeldata at the time of frame inverting drive achieved by the drive shown inFIG. 9.

FIG. 14 is a block diagram showing another example of the dataprocessing block of the image display apparatus shown in FIG. 1.

FIG. 15 is a block diagram showing still another example of the dataprocessing block of the image display apparatus shown in FIG. 1.

FIG. 16 is a block diagram showing a further example of the dataprocessing block of the image display apparatus shown in FIG. 1.

FIG. 17 is a block diagram showing a still a further example of the dataprocessing block of the image display apparatus shown in FIG. 1.

FIG. 18 is a characteristic diagram for explanation of the relationshipbetween panel drive signal V(i) and video signal V1(i) in the dataprocessing block shown in FIG. 17.

FIG. 19 is a diagram showing the state where select signals of the imagedisplay apparatus are changed in synchronization with a horizontalsynchronization signal and a vertical synchronization signal.

FIG. 20 is a diagram showing the state of a display made by the selectsignals shown in FIG. 19.

FIG. 21 is a diagram outlining a projection type image display apparatus(projector) to which the present invention is applied.

FIG. 22A is a block diagram showing the configuration of a conventionalimage display apparatus which performs phase expansion, and FIG. 22B isa timing chart of the operation of this apparatus.

FIG. 23 is a block diagram showing an example of an arrangement usingselectors to perform one-dot polarity inverting drive in the imagedisplay apparatus shown in FIG. 22A.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Embodiments of the present invention will be described with reference tothe drawings.

First Embodiment

FIG. 1 schematically shows an image display apparatus to which thepresent invention has been applied. In the following description,elements having the functions common to this image display apparatus andthe image display apparatus described above with reference to FIG. 6 areshown with the same reference characters.

Referring to FIG. 1, the image display apparatus is a display apparatusof a type using an active matrix type liquid crystal panel 110, and isconstituted mainly of a liquid crystal panel block 100, a timinggeneration circuit block 200 and a data processing circuit block 300.

The liquid crystal panel block 100 has, on the same glass substrate, aliquid crystal panel 10, which is an image display unit, a scanning-sidedrive circuit 120, which is a scanning signal line selection means, anda data-side drive circuit 130, which is a signal supply means.

In the liquid crystal panel 10, pixels 116 connected to a plurality ofdata signal lines 112 and to a plurality of scanning signal lines 114are arrayed in matrix form. Each pixel 116 is formed of a switchingelement, e.g., a thin film transistor (TFT) 116a and a liquid crystallayer 116b. Switching element 116a is not limited to a threeterminalelement represented by TFT and may alternatively be a two-terminalelement represented by a metal layer-insulating layer-metal layer (MIM)element. An application of the present invention, to drive a liquidcrystal panel, the kind of liquid crystal panel is not limited to theabove-described active matrix panel and may also be a simple matrixliquid crystal panel, and switching element 116a is not alwaysnecessary.

The scanning-side drive circuit 120 supplies scanning signals to thescanning signal lines 114 to successively select the scanning signallines 114.

The data-side drive circuit 130 has, for example, six signal supplylines 132, a plurality of sampling switches 134 connected between thesix signal supply lines 132 and the plurality of data signal lines 112,and a shift register 136 which outputs signals to the sampling switches134 to determine sampling timing.

The timing generation block 200 is arranged to supply various timingsignals to the liquid crystal panel block 100 and to the data processingcircuit block 300. Details of the timing generation block 200 will bedescribed later.

As shown in FIG. 2, the data processing circuit block 300 has, as itsmain constituents, a first phase expansion circuit 310, a branchingcircuit 330, a selection circuit 340, a digital-to-analog conversioncircuit 350, a gamma correction circuit 360, a clamp circuit 370, asecond phase expansion circuit 380, and a connection change circuit(rotation circuit) 390.

The configuration of the data processing block 300 will be described inmore detail along with the operation thereof.

To the first phase expansion circuit 310 are input, for example, digitalpixel data a1, a2, a3 . . . to be supplied to pixels 116 connected tothe first-line scanning signal line 114 and digital pixel data b1, b2,b3 . . . to be supplied to second-line pixels 116, as shown in FIG. 2.

The first phase expansion circuit 310 has a first latch circuit 312a anda second latch circuit 312b to each of which the above-mentioned digitalpixel data is input. As shown in FIGS. 3A and 3B, the first latchcircuit 312a and the second latch circuit 312b have the sameconfiguration and each have first and second AND circuits 314 and 316,an OR circuit 318 and a flip-flop 320.

To the first AND circuit 314 of the first or second latch circuit 312a,a frequency-divided clock S (having a frequency of, for example, 20 MHz)obtained by frequency-dividing a reference clock CLK (having a frequencyof, for example, 40 MHz) or an inverted clock S which is the inverse ofthe clock S is input from the timing generation circuit block 200. Thetiming generation circuit block 200 controls, according to a horizontalscanning signal and/or a vertical scanning signal, change of thecircuits to which frequency-divided clock S and inverted clock S areinput in such a manner that, when frequency-divided clock S is input tothe first latch circuit 312a, the corresponding inverted clock S isinput to the second latch circuit 312b. In this sense, the timinggeneration block 200 functions as a change control means for controllingchange of the phase expansion order in the first phase expansion circuit310.

To the OR circuit 318, outputs from the first and second AND circuits314 and 316 are input. An output from the OR circuit 318 is supplied toa D terminal of the flip-flop 320. To a clock terminal C of theflip-flop 320, reference clock CLK is input. These reference clock 200,frequency-divided clock C, inverted frequency-divided clock S aresupplied from the timing generation circuit 200 to the flip-flop 320.

If, for example, frequency-divided clock S is input to the first latchcircuit 312a, the first latch circuit 312a latches data al by a fall offrequency-divided clock S, as shown in FIG. 4. When frequency-dividedclock S becomes LOW, the output of the second AND circuit 314 becomesHIGH simultaneously, thereby sustaining the latched data al as Q output.This operation is continued until data a3 is latched by the next fall offrequency-divided clock S. Thus, in the first latch circuit 312a, dataa1, a3, a5 . . . are latched and phase-expanded so that the data lengthis twice the original length. An output signal from the first latchcircuit 312a thus obtained will be referred to as digital phase-expandedsignal D1. In the above-described case, in the second latch circuit 312bto which inverted frequency-divided clock S is input, data a2, a4, a6 .. . are also latched and phase-expanded so that the data length is twicethe original length and are output by being delayed by the period of onecycle of reference clock CLK (half period of frequency-divided clock S),as shown in FIG. 4. An output signal from the second latch circuit 312bthus obtained will be referred to as digital phase-expanded signal D2.

The branching circuit 330 has, as shown in FIG. 2, first and secondbranch lines 332a and 332b to which digital phase-expanded signal D1 issupplied, and third and fourth branch lines 332c and 332d to whichdigital phase-expanded signal D2 is supplied. A buffer 334 is connectedto each of the first and third branch lines 332b and 332d to directlyoutput digital phase-expanded signal D1 or D2. An inverter 336, forexample, is connected to each of the second and fourth branch lines 332band 332d to output digital phase-expanded signal D1 or D2 whileinverting the polarity of the signal.

As a method of inverting the polarity of a digital signal, one of amethod of inverting the logical state of digital values, and a method ofobtaining the 2's complement of binary digital values, for example, maybe used. In the former method, 2-bit data (11) is replaced with (00),for example. In the latter method, 2-bit data (11) is replaced with(01). In this manner, the polarity of voltages applied to pixels 116 canbe inverted relative to the scanning signal. One of these two oppositepolarities will be referred to as a first polarity, e.g., a positivepolarity and the other is referred to as a second polarity, e.g., anegative polarity. To invert the polarity of the voltage applied to eachpixel 116 in the case where, for example, the switching element 116a isformed of TFT, the potential of the data signal may be changed relativeto the potential of the opposed (common) electrode. If the switchingelement 116a is formed of, for example MIM, the polarity may be changedby changing the potential of the scanning signal relative to a mediumpotential of the amplitude of data signals.

In this specification, signals obtained by polarity inversion fromdigital signals D1 and D2 are represented by D1 and D2. Also, analogsignals respectively obtained by digital-to-analog conversion fromdigital signals D1, D2, D1, and D2 are represented by A1, A2, A1 and A2.These inverted signals D1, D2, and A1 and A2 correspond to thoseindicated with symbols D1, D2, A1, and A2 with upper bars in thediagram.

Digital phase-expanded signal D1 is output through the first branch line332a, inverted signal D1 of digital phase-expanded signal D1 through thesecond branch line 332b, digital phase-expanded signal D2 through thethird branch line 332c, and inverted signal D2 of digital phase-expandedsignal D2 through the fourth branch line 332d.

The selection circuit 340 has a first digital switch 342 which connectsto one of the first and second branch lines 332a and 332b, and a seconddigital switch 344 which connects to one of the third and fourth branchlines 332c and 332d.

The digital-to-analog conversion circuit 350 has a firstdigital-to-analog conversion circuit 352 for digital-to-analogconversion of digital phase-expanded signal D1 or D1, which is inputthrough the first digital switch 342, and a second digital-to-analogconversion circuit 354 for digital-to-analog conversion of digitalphase-expanded signal D2 or D2, which is input through the seconddigital switch 344. Each of the first and second digital-to-analogconversion circuits 352 and 354 performs, for digital-to-analogconversion, data sampling by sampling timing on the basis offrequency-divided clock S, so that a small size and a low price of thecircuit can be maintained.

An output from the first digital-to-analog conversion circuit 352 willbe referred to as a first phase-expanded analog signal A1 (or A1), andan output from the second digital-to-analog conversion circuit 354 willbe referred to as a first phase-expanded analog signal A2 (or A2).

The gamma correction circuit 360 and the clamp circuit 370 are connectedto output lines from the first and second digital-to-analog conversioncircuits 352 and 354. In the gamma correction circuit 360, a firstpositive gamma correction circuit 362 and a first negative gammacorrection circuit 364 are connected to the output line from the firstdigital-to-analog conversion circuit 352 while a second positive gammacorrection circuit 366 and a second negative gamma correction circuit368 are connected to the output line from the second digital-to-analogconversion circuit 354. In the clamp circuit 370, a first positive clampcircuit 372 and a first negative clamp circuit 374 are connected to theoutput line from the first digital-to-analog conversion circuit 352while a second positive clamp circuit 376 and a second negative clampcircuit 378 are connected to the output line from the seconddigital-to-analog conversion circuit 354. These gamma correctioncircuits 362 to 368 and clamp circuits 372 to 378 are the same aswell-known ones and, therefore, will not be explained.

The second phase expansion circuit 380 has six, first to sixth sampleand hold circuits 381 to 386. First phase-expanded analog signal A1 (orA1) is constantly supplied via the first digital-to-analog circuit 352to the odd-numbered sample and hold circuits 381, 383, and 385 in thesecond phase expansion circuit 380. On the other hand, secondphase-expanded analog signal A2 (or A2) is constantly supplied via thesecond digital-to-analog circuit 354 to the even-numbered sample andhold circuits 382, 384, and 386 in the second phase expansion circuit380. As shown in FIG. 4, sampling clocks SHCL1 to SHCL6 which determinephase expansion order are input to the first to sixth sample and holdcircuits 381 to 386 to further N-phase-, e.g., 3-phase-expand the firstphase-expanded analog signal. Since the signal has already beenn-phase-, e.g., 2-phase-expanded, the signal is expanded in n X N=6phases in comparison with the data length of the original pixel data.

Six clocks SHCL1 to SHCL6 are provided, as shown in FIG. 5. Clocks SHCL1to SHCL6 are generated on the basis of select signals S1 to S6 in thetiming generation circuit block 200. In this apparatus, six samplingclocks SHCL1 to SHCL6 supplied are changed in accordance with ahorizontal sync signal and a vertical sync signal in driving the liquidcrystal panel 110. In the timing generation circuit 200, therefore, asexenary counter 210 and a binary counter 212 are provided, as shown inFIG. 6. The sexenary counter 210 counts pulses of the horizontalscanning signal. The binary counter 212 counts pulses of the verticalscanning signal. A line controller 214, which is supplied with outputsfrom these two counters 210 and 212, successively outputs select signalsS1 to S6 by changing these signals one to another each time the sexenarycounter 210 counts, in other words, when each horizontal scan (1H) ismade by newly selecting one of the scanning signal lines 114 shown inFIG. 1. The line control 214 can also change the select signals S1 to S6output order each time the binary counter 212 counts, in other words,when one-frame drive of the liquid crystal display shown in FIG. 1 isperformed and when each vertical scan (1V) is started. For example, theline control 214, having output the select signals from S1 for the firstframe, can start outputting the select signals from S2 for the secondframe. Six sampling clocks SHCL1 to SHCL6 are generated in a samplingclock generation circuit 216, to which select signals S1 to S6 areinput. A circuit for determining one of frequency-divided clock S andinverted clock S supplied to the first and second latch circuit 312a or312b of the first phase expansion circuit 310 is provided in the timinggeneration circuit block 200, although it is not illustrated in thecircuit diagram.

Outputs from the first to sixth sample and hold circuits 381 to 386,supplied to phase-expanded signal output lines 388a to 388f will bereferred to briefly as V1 to V6. With respect to a rearrangement ofthese outputs V1 to V6 at pixel positions, four drive methods shown inFIGS. 7 to 10 are conceivable.

Referring to FIG. 7, the sampling order is changed in accordance withselect signal S1 with respect to first line of each of frames 1 and 2,select signal S2 with respect to the second line, select signal S3 withrespect to the third line, . . . and select signal S6 with respect tothe sixth line. This is done recursively with respect to the subsequentlines. If the number of lines in one frame is a multiple of 6, repeatingthis cycle results in same sampling order with respect to the secondframe. The sexenary counter 210 may be reset at the end of one frameirrespective of whether or not the number of lines in one frame is amultiple of 6, thereby setting the same expansion order with respect tothe first and second frames.

Signs "+" and "-" in FIG. 7 designate polarities of data sampled andheld. Dot inverting drive such as shown in FIG. 7 can be performed byoperating the first and second digital switches 342 and 344 by thesignals from the timing generation circuit 200. FIG. 11 shows the resultof replacement of the contents of FIG. 7 with pixel data.

Referring to FIGS. 8 and 9, changes in sampling order are the same asthose shown in FIG. 7 but the first and second digital switches 342 and344 are changed in a different manner. The contents of FIG. 8 correspondto line inverting drive and the result of replacement of the contents ofFIG. 8 with pixel data are as shown in FIG. 12. On the other hand, thecontents of FIG. 9 correspond to frame inverting drive and the result ofreplacement of the contents of FIG. 9 with pixel data are as shown inFIG. 13.

FIG. 10 shows the method most favorable in terms of displaycharacteristics. The frame 1 of FIG. 10 is the same as the frame 1 ofFIG. 7 but frame 2 of FIG. 10 is different from frame 2 of FIG. 7. Inthe method shown in FIG. 10, the sampling order at the first line offrame 2 is made different from that in frame 1 such that the first lineof frame 2 is the same as the second line of frame 1. That is, while theexpansion order is successively changed starting from select signal S1with respect to frame 1, the expansion order is successively changedstarting from select signal S2 with respect to frame 2. This operationis shown as dot inverting drive in FIG. 11 by replacement with pixeldata.

In the connection change circuit 390, the connection between sixphase-expanded signal output lines 388a to 388f and six signal supplylines 132a to 132f is changed so that pixel data is supplied as shown inFIGS. 11 to 13. It is necessary to perform this changing insynchronization with the above-described change of the phase expansionorder in the first and second phase expansion circuits 310 and 380. Theconnection is selected from six modes shown in FIG. 5. By this changing,each of the dot inverting drive, the line inverting drive and the frameinverting drive shown in FIGS. 11 to 13 can be realized. From theviewpoint of the life of the liquid crystal, the dot inverting driveshown in FIG. 11 is considered to be the best.

Each drive, however, is advantageous in that, even if the gains of theamplifiers of the first to sixth sample and hold circuits 381 to 386vary, for example, the gain of one of the amplifiers is higher, brighterpixels can be obliquely dispersed to become visually unnoticeable bybeing prevented from being arrayed continuously in the verticaldirection on the liquid crystal panel 110 as in the case of theconventional art. In particular, if the changing method shown in FIG. 10is used, a further improvement in image quality can be achieved becausethe sampling order is also changed with respect to frames to change thepositions of brighter pixels.

To obtain various control signals for realizing the phase expansionorder in the first and second phase expansion circuits 310 and 380 foreach of the methods shown in FIGS. 7 to 11, the combination ofconnection changes in the changing circuit 390 required simultaneously,and the switching operation of the first and second digital switches 342and 344 also required simultaneously, the corresponding modes may bestored in a memory, for example, and a user may select each mode bysupplying a signal to an external terminal of an IC. Alternatively,selection of each mode may be enabled as an internal change in an IC ina factory producing the IC.

Second Embodiment

FIG. 14 shows a more preferable data processing circuit block 400, whichcan be used in place of the data processing circuit 300 shown in FIG. 1.The data processing circuit block 400 shown in FIG. 14 differs from thedata processing circuit 300 in that it has a polarity determinationcircuit 410 in place of the branching circuit 330 and the selectioncircuit 340 shown in FIG. 2, and that a gamma correction circuit 420 anda clamp circuit 430 are provided in place of the gamma correctioncircuit 360 and the clamp circuit 370 shown in FIG. 2.

The polarity determination circuit 410 has a buffer 412 which directlyoutputs digital phase-expanded signal D1 from the first latch circuit312a, and an inverter 414 which inverts digital phase-expanded signal D2from the second latch circuit 312b and outputs the inverted signal.Therefore, digital phase-expanded signal D1 and the digitalphase-expanded signal D2 are constantly output from the buffer 412 andthe inverter 414, respectively.

The gamma correction circuit 420 has a positive gamma correction circuit422 for executing positive gamma correction of the output from thebuffer 412, and a negative gamma correction circuit 424 for executingnegative gamma correction of the output from the inverter 414.Similarly, the clamp circuit 430 has a positive clamp circuit 432 forclamping an output from the positive gamma correction circuit 422 withpositive polarity, and a negative clamp circuit 434 for clamping anoutput from the negative gamma correction circuit 424 with negativepolarity.

Thus, the data processing circuit 400 shown in FIG. 14 has a smallernumber of circuits in comparison with the data processing circuit 300shown in FIG. 2.

In this second embodiment, data outputs shown in FIG. 10 can be obtainedas outputs from the second phase expansion circuit 380 in a simplemanner while the number of circuits is reduced, and dot inverting driveshown in FIG. 11, which is favorable in terms of liquid crystal lifecharacteristics, can be performed.

Third Embodiment

FIG. 15 shows another data processing circuit block 500, which can beused in place of the data processing circuit 300 shown in FIG. 1. Thedata processing circuit block 500 shown in FIG. 15 is formed in such amanner that the first phase expansion circuit 310 shown in FIG. 2 isremoved and a digital-analog circuit 510 is provided in place of thedigital-to-analog conversion circuit 350 shown in FIG. 2.

This digital-analog circuit 510 has a first digital-to-analog conversioncircuit 512 which performs digital-to-analog conversion of pixel data ofpositive or negative digital signal DIN or DIN selected by the firstdigital switch 342 to output a first analog signal A1 or A1, and a firstdigital-to-analog conversion circuit 514 which performsdigital-to-analog conversion of positive or negative digital signal DINor DIN selected by the second digital switch 344 to output a secondanalog signal A2 or A2.

These first and second digital-to-analog circuits 512 and 514 may have afunction of sampling and holding odd or even pixel data of a digitalsignal, as does the circuit shown in FIG. 3, to output firstphase-expanded analog signals A1 (A1) and A2 (A2) having a data lengthtwice as long as the original data length, as are those shown in FIG. 2.Thus, the first and second digital-to-analog conversion circuit 512 and514 may also have the function of the first phase expansion circuit 310.In such a case, the subsequent data processing is the same as that inthe case shown in FIG. 2, and 3-phase expansion may be performed by thesecond phase expansion circuit 380. If the first and seconddigital-analog circuits 512 and 514 have no sample and hold function,6-phase expansion may be performed by only one phase expansion circuit,i.e., the second phase expansion circuit 380.

In this third embodiment, therefore, each of the four patterns of dataoutputs shown in FIGS. 7 to 10 can be obtained as outputs from thesecond phase expansion circuit 380, thus enabling the various invertingdrives shown in FIGS. 11 to 13.

Fourth Embodiment

FIG. 16 shows still another data processing circuit block 600, which canbe used in place of the data processing circuit 300 shown in FIG. 1. Thedata processing circuit block 600 shown in FIG. 16 differs from the dataprocessing circuit 500 shown in FIG. 15 in that it has the polaritydetermination circuit 410 described above with reference to FIG. 14 inplace of the branching circuit 330 and the selection circuit 340 shownin FIG. 15, and that the gamma correction circuit 420 and the clampcircuit 430 described above with reference to FIG. 14 are provided inplace of the gamma correction circuit 360 and the clamp circuit 370shown in FIG. 15.

Thus, the difference of the operation of the circuits shown in FIG. 16from that of the circuits shown in FIG. 15 is the same as the differencebetween the operations of the circuits shown in FIGS. 2 and 14.Consequently, in this fourth embodiment, each of the two patterns ofdata outputs shown in FIGS. 7 and 10 can be obtained in a simple mannerwhile the number of circuits is reduced, thus enabling the dot invertingdrive shown in FIG. 11, which is favorable in terms of liquid crystallife characteristics.

Fifth Embodiment

FIG. 17 shows a further data processing circuit block 700, which can beused in place of the data processing circuit 300 shown in FIG. 1. Thedata processing circuit block 700 shown in FIG. 17 is supplied with ananalog video signal VIDEO unlike from those of the above-describedembodiments. This data processing circuit block 700 has a polarityinversion circuit 710, a phase expansion circuit 720, a rotation circuit730, and a control circuit 740 for controlling these circuits.

As shown in FIG. 17, the polarity inversion circuit 710 has a signaloutput circuit 712 which forms two signals: a video signal of a normalpolarity (positive signal) and a video signal of an inverse polarity(negative signal) from input video signal VIDEO, and which outputs thetwo signals formed. These two signals are inverse in polarity relativeto each other so that, for example, a medium potential between theirblack levels is a common potential.

The video signal of the positive polarity VIDEO (+) in the signalsoutput from the signal output circuit 712 is constantly supplied toodd-numbered sample and hold circuits 722a, 722c, and 722e of the phaseexpansion circuit 720 described below while the video signal of thenegative polarity VIDEO (-) in the signals output from the signal outputcircuit 712 is constantly supplied to even-numbered sample and holdcircuits 722b, 722d, and 722f of the phase expansion circuit 720described below. When input video signal VIDEO is phase-expanded,sampling start times are set alternately for the odd-numbered sample andhold circuits and the even-numbered sample and hold circuits asexpansion order. The odd phases and even phases are thereby made alwaysopposite in polarity from each other. In this manner, occurrence ofcrosstalk in the horizontal direction can be prevented.

In the phase expansion circuit 720, the order in which input videosignal VIDEO is phase-expanded by the sample and hold circuits 722a to722f (phase expansion order) is shifted by the timing of the horizontalsync signal. Also, in the rotation circuit 730, the combination ofconnections between the output lines from the sample and hold circuits722a to 722f and output terminals OUT1 to OUT6 with respect to the sixsignal supply lines 132a to 132f is shifted by the timing of thehorizontal sync signal. As a result, the potentials applied to thepixels of the liquid crystal panel 110 are also inverted in polaritybetween each adjacent pair of pixels arranged in the vertical direction,thereby preventing occurrence of crosstalk in the vertical direction aswell as in the horizontal direction.

The phase expansion circuit 720 is arranged to expand input video signalVIDEO in six phases by using six sample and hold circuits 722a to 722f.The six sample and hold circuits 722a to 722f sample pixel signals ininput video signal VIDEO in accordance with sample signals supplied froman expansion order designation circuit 726 to the sample and holdcircuits 722a to 722f; each of the sample and hold circuits 722a to 722fsamples the pixel signal of input video signal VIDEO supplied to it whenit is supplied with one of the sample signals, and holds the sampledsignal until it is supplied with the next sample signal. Thus, the pixelsignals contained in input video signal VIDEO is expanded in six phases,as described above with reference to FIG. 6(b), thereby extending thedata length per pixel. Thus, the frequency of panel drive video signalsV(i) (i=1 to 6) supplied from output terminals OUT1 to OUT6 to thesignal supply lines 132a to 132f after being passed through the rotationcircuit 730 can be reduced. With respect to the data-side drive circuit130, there is a need to sufficiently increase the time period throughwhich the liquid crystal layer 116b is charged and, hence, a need toreduce the operating speed of the data-side drive circuit 130. It is,therefore, possible to effect matching between the operating speed ofthe data-side drive circuit 130 and the frequency of input video signalVIDEO in the liquid crystal panel 110 in which the data-side drivecircuit 130 is formed along with TFTs 116a on the glass substrate. As aresult, even if the liquid crystal panel 110, in which the operatingspeed of the data-side drive circuit 130 is not so high, is used as adisplay unit, a high-quality image can be displayed at a highresolution. The phase expansion circuit 720 described above can beformed of sample and hold circuits which sample and hold pixels signalsin the analog form with respect phases, as in this embodiment. If pixelsignals formed as digital signals are input, latch circuits, such asthose shown in FIG. 3, which latch data with respect to phases, may beused. In the first and second embodiments, phase expansion is executedat two stages, that is, digital signal phase expansion and analog signalphase expansion are performed. However, one-stage analog signal phaseexpansion, performed in this embodiment, or one-stage digital signalphase expansion may alternatively be performed.

However, if the combination of panel drive video signal V(i) and thecircuits of the channels in the phase expansion circuit 720 iscompletely fixed, a difference in a circuit characteristic such as gainmay occur due to a non-uniformity of the environment around the phaseexpansion circuit 720 or the elements constituting the circuits to causevertical line unevenness.

In the image display apparatus of this embodiment, therefore, therotation circuit 730 is provided as connection changing means to preventoccurrence of such vertical line unevenness. That is, the rotationcircuit 730 has a rotation control circuit 732, and six 6-inputone-output analog switches 734a to 734f. To the rotation control circuit732, timing signals are input from the timing generation circuit block200. In accordance with the timing signals, the rotation control circuit732 outputs, to each of the analog switches 734a to 734f, a selectsignal which designates one of the sample and hold circuits 722a to 722fof the phase expansion circuit 720 holding one of video signals V1(i) tobe selected and output. Each of the analog switches 734a to 734f selectsone of video signals V1(i) held by the sample and hold circuits 722a to722f in accordance with the select signal applied to it. The rotationcontrol circuit 732 for generating such select signals can be realizedby using counters 210 and 212 provided in the timing generation circuit200 described above with respect to the example shown in FIG. 6, or thelike.

The rotation control circuit 732 holds several unit combinations ofvideo signals V1(i) and panel drive video signals V(i), i.e.,combinations of the sample and hold circuits 722a to 722f and the outputterminals OUT1 to OUT6, and changes these combinations by predeterminedtiming.

In this embodiment, the rotation control circuit 732 has six sets ofselection signals S1 to S6 and changes these signals in synchronizationwith the video display horizontal sync signal. In this case, therelationship between select signals S1 to S6 at the analog switches 734ato 734f and the inputs and outputs (combinations of panel drive signalsV(i) and video signals V1(i)) is as shown in FIG. 18. FIG. 18 shows thestate where video signals V1(i) held by the sample and hold circuits722a to 722f to be output as panel drive signals V(i) are changed insynchronization with the horizontal sync signal by select signals S1 toS6.

However, in order to change the combination of video signals V1(i) heldby the sample and hold circuits 722a to 722f and panel drive videosignals V(i) by select signals S1 to S6 in the rotation circuit 730, itis necessary to previously change the order in which the sample and holdcircuits 722a to 722f hold input video signal VIDEO so that apredetermined one of the data signal lines 112 is supplied with a pixelsignal correctly assigned to it. Such expansion order control isperformed by the expansion order designation circuit 726 based on thetiming of changing select signals S1 to S6. That is, a control circuit702 controls the expansion order designation circuit 726 and therotation control circuit 732 in cooperation with the timing signals.

In the thus-arranged image display apparatus, reference clock signal CLKand synchronization signal SYNC are input to the timing generationcircuit block 200, and the timing signals including the clock foroperating each circuit block are output from the timing generationcircuit block 200.

In the data processing circuit block 700, 6-phase expansion of inputvideo signal VIDEO is performed by the phase expansion circuit 720, andphase-expanded video signals V1(i) are held by the sample and holdcircuits 722a to 722f.

Phase-expanded video signals V1(i) undergo rotation processing in therotation circuit 730 to become panel drive video signals V(i). Thesepanel drive video signals V(i) are output to the signal supply lines132a to 132f via the output terminals OUT1 to OUT6 and the inputterminals VIN1 to VIN6. The data-side drive circuit 130 samples, in thesampling switches 134, panel drive video signals V(i) in the respectivephases appearing in the signal supply lines 132a to 132f by the samplingsignals formed by the shift register 136 on the basis of the signalsfrom the timing generation circuit block 200, and outputs predeterminedpotentials to the data signal lines 114.

During this operation, select signals S1 to S6 output from the rotationcontrol circuit 732 change as shown in FIG. 19. For example, selectsignals S1 to S6 change in the order of S1, S2, S3, S4, S5, S6 . . .with respect to one frame in synchronization with the horizontal syncsignal of the video signal, and change recursively in this order.

Such order may also be changed in synchronization with the vertical syncsignal of the video signal. That is, for the next picture, selectsignals S1 to S6 change in the order of S6, S1, S2, S3, S4, S5, . . .with respect to one frame in synchronization with the horizontal syncsignal of the video signal, and change recursively in this order.

As shown in FIG. 20, in the liquid crystal panel 102, at the first line,panel drive video signals V(i) are output in the order of video signalsV1(1), V1(2), V1(3), V1(4), V1(5), V1(6) for display on the six pixelsarranged in the horizontal direction. Then, at the second line, paneldrive video signals V(i) are output in the order of video signals V1(6),V1(1), V1(2), V1(3), V1(4), V1(5) for display on the respective pixels.

With respect to the next picture, at the first line, panel drive videosignals V(i) are output in the order of video signals V1(6), V1(1),V1(2), V1(3), V1(4), V1(5) for display on the six pixels arranged in thehorizontal direction. Then, at the second line, panel drive videosignals V(i) are output in the order of video signals V1(5), V1(6),V1(1), V1(2), V1(3), V1(4) for display on the respective pixels.

It is assumed here that one of the six sample and hold circuits 722a to722f, for example, the sample and hold circuit 722a, has a gain lowerthan the gains of the others. In such a case, even if even-level inputvideo signal VIDEO for a picture is input to make a display uniform inbrightness through the entire picture, the strength of video signalV1(1) held by the sample and hole circuit 722a having a smaller gain islow, so that the pixels to which this signal is supplied as panel drivevideo signal V(i) are lower in display brightness than the others. Inthis embodiment, however, the combination of video signal V1(i) andpanel drive video signal V(i) is shifted in synchronization with thehorizontal sync signal by the rotation circuit 730. As a result, thepixels differing in brightness on the liquid crystal panel 110 areobliquely dispersed without being aligned on a vertical line, as shownin FIG. 20. Thus, an intrinsic difference between the sample and holdcircuits 722a to 722f is displayed by being dispersed in one picture onthe liquid crystal panel 110, and no vertical line non-uniformityappears on the liquid crystal panel 110.

Even if an oblique line display non-uniformity occurs, the position ofthe non-uniformity is changed each time the picture is changed, as shownin FIG. 20, because the select signals are changed in synchronizationwith the vertical sync signal. Therefore, the influence of acharacteristic difference between sample and hold circuits or the likeappearing when phase expansion is performed by the circuits can also bedispersed with respect to time, thus making it possible to obtainhigh-quality high-resolution images.

Further, the select signals are changed to invert the polarities ofpanel drive video signals so that the polarities between each ofadjacent pairs of pixels in the horizontal and vertical directions arealways opposite from each other, thereby preventing crosstalk betweeneach adjacent pair of pixels. According to the present invention, suchone-dot polarity inverting display is achieved by the method essentiallybased on the combination of video signal V1(i) and panel drive videosignal V(i). That is, it is not necessary for the polarity inversioncircuit 710 to use selectors 42a and 42b formed of analog switches asshown in FIG. 22. The apparatus is therefore free from the need forhandling video signals VIDEO (+) and (-) having a high frequency withanalog switches, and can be simplified in circuit configuration. In thecase where digital signals undergo phase expansion, the polarity of thesignals is fixed with respect to each of the signal phases and,therefore, analog gamma correction and clamp processing for the signalof each polarity may suffice, so that the circuit configuration can besimplified.

In this embodiment, while the phase expansion circuit 720 is arranged soas to be able to expand input video signal VIDEO in six phases by usingsix sample and hold circuits 722a to 722f, it is, of course, possible toset a number of phases different from 6. Preferably, the number ofphases is matched with the number of signal lines. Six-phase expansion,however, is advantageous in that, in the full-color liquid crystal panel110, the same signal supply line 132 can be connected to the data signallines 112 to pixels of the same color arranged in the horizontaldirection.

After phase expansion, there is also a possibility of occurrence of adifference between offsets between the inputs and outputs of the analogswitches in the rotation circuit 730. Ordinarily, such a difference issufficiently small in comparison with those of the image signal holdingcircuits and amplifier circuits in the phase expansion circuit 720.Therefore, if the rotation circuit 730 is provided, a voltage differencebetween panel drive video signals V(i), i.e., a difference between thedegrees of brightness on the pixels of the liquid crystal panel 110, canbe reduced and the image quality improvement effect of the rotationprocessing is sufficiently high.

The relationship between select signals S1 to S6 or S1 to S3 at theanalog switches and the combinations of phase-expanded video signalsV1(i) and panel drive signals V(i) is not limited to that shown in FIG.18. Any other conditions are possible as long as one-dot invertingdisplay can be performed on the display unit by using the phase-expandedvideo signals.

The rotation circuit 730 or the data processing circuit block 700including the rotation circuit 730 may be formed on a glass substrateoutside the liquid crystal panel block 100 and may be formed in an IC.The rotation circuit 730 can be used in such an IC to eliminate the needfor level adjustment between the channels of the signal processingcircuits for phase expansion. Also, high-quality images can be obtainedwithout any considerable problem even if there is a slight difference inlevel between the sample and hold circuits when these circuits areintegrated in the IC. Thus, the above-described circuits can easily beintegrated in an IC.

Sixth Embodiment

The first to fifth embodiments have been described with respect to animage display apparatus using liquid crystal panel 110 as an imagedisplay unit. Needless to say, an apparatus using electroluminescentelements, a CRT or the like as a display unit is also possible.

Further, a projection type image display apparatus using liquid crystalpanel 110 as a light valve may also be formed, as described below.

FIG. 21 schematically shows a projection type image display apparatus(projector) using a three-plate prism type optical system.

In the projector 1100 shown in FIG. 21, light projected from a whitelight source lamp unit 1102 is separated into three primary colors R, G,and B in a light guide 1104 by a plurality of mirrors 1106 and twodichroic mirrors 1108. Primary color light is led to three TFT liquidcrystal panels 1110R, 1110G, and 1110B for displaying images in thecorresponding colors. Light modulated with the TFT liquid crystal panels1110R, 1110G, and 1110B is incident upon a dichroic prism 1112 in threedirections. In the dichroic prism 1112, R light and B light are bentthrough 90° while G light travels straight. Images in the differentcolors are thereby combined into a multicolor image, which is projectedonto a screen or the like by a projection lens 1114. If video signalsprocessed in one of the data processing circuit blocks 300 to 700 havingthe phase expansion function and the rotation function in accordancewith the above-described embodiments are respectively supplied to theliquid crystal panels 1110R, 1110G, and 1110B, images in thecorresponding colors can be formed as high-quality high-resolutionimages by the liquid crystal panels 1110R, 1110G, and 1110B. Therefore,a large image free from horizontal crosstalk and vertical linenon-uniformity and having high resolution can be projected onto a screenor the like by using the projector 1100.

The present invention is not exclusively applied to the above-describedimage display apparatus arranged as a projector having transmission typeliquid crystal panel. The present invention can be applied to any othervideo display apparatuses, e.g., a projector using a reflection typeliquid crystal panel, a vehicle navigation apparatus, touch panelapparatus, a POS terminal, a video camera or a video apparatus with amonitor, a television set, a personal computer, a word processor, and aportable telephone set.

What is claimed is:
 1. An image display apparatus having:an imagedisplay unit in which pixels electrically connected to a plurality ofdata signal lines and to a plurality of scanning signal lines arearrayed in a matrix form; and scanning signal line selection means forsupplying said scanning signal lines with scanning signals forsuccessively selecting said scanning signal lines, said apparatusdriving said pixels by applying voltages to the pixels in accordancewith said data signals and said scanning signals while inverting thepolarities of the voltages applied to the pixels, said apparatuscomprising:phase expansion means supplied with a first video signalhaving serial pixel data for driving said pixels by voltages having afirst polarity, and with a second video signal having serial pixel datafor driving said pixels by voltages having a second polarity, said phaseexpansion means forming, from said first and second video signals, m(where m is an integer equal to or larger than 2) phase-expanded signalsexpanded into pixel data by extending the data length of items of saidpixel data corresponding to some of said pixels periodically selected,said phase expansion means outputting the phase-expanded signals tophase-expanded signal output lines in parallel with each other, whereinsaid phase expansion means has m sample and hold sections connected tosaid m phase-expanded signal output lines, said first video signal beingconstantly input to one of two groups of said sample and hold sectionsduring a frame period, said second video signal being constantly inputto the other group of said sample and hold sections during the frameperiod; signal supply means for supplying said pixel data to saidplurality of data lines on the basis of said m phase-expanded signalsinput via m signal supply lines; connection change means for changingconnections between said m phase-expanded signal output lines and said msignal supply lines; and change control means for controlling change ofthe order of expansion into said in phase-expanded signals performed bysaid phase expansion means, and a combination of connections changed bysaid connection change means by linking the combination to saidexpansion order, wherein said change control means performs changecontrol so that an expansion order first set with respect to thepreceding frame is changed to a different expansion order insynchronization with vertical synchronization.
 2. An image displayapparatus according to claim 1, wherein said change control meanscontrols change of said expansion order between at least m expansionorders in accordance with a predetermined sequence and insynchronization with horizontal synchronization.
 3. An image displayapparatus according to claim 1, wherein said change control means formssaid m expansion signals by alternately expanding said pixel data ofsaid first and second video signals.
 4. An image display apparatusaccording to claim 1, wherein said image display unit comprises a liquidcrystal panel, and said signal supply means comprises a data-side drivesection which supplies said pixel data to said data signal lines of saidliquid crystal panel.
 5. An image display apparatus according to claim1, wherein said image display unit comprises a projection type displayunit having a liquid crystal panel and a projection light source, andsaid signal supply means comprises a data-side drive section whichsupplies said pixel data to said data signal lines of said liquidcrystal panel.
 6. An image display apparatus having:an image displayunit in which pixels electrically connected to a plurality of datasignal lines and to a plurality of scanning signal lines are arrayed ina matrix form; scanning signal line selection means for supplying saidscanning signal lines with scanning signals for successively selectingsaid scanning signal lines; and signal supply means for supplying pixeldata signals to said plurality of data signal lines, said apparatusdriving said pixels by applying voltages to the pixels in accordancewith said data signals and said scanning signals while inverting thepolarities of the voltages applied to the pixels, said apparatuscomprising:first phase expansion means supplied with a digital signalhaving pixel data of a first data length corresponding to the positionof each of said pixels, said first phase expansion means outputting twophase-expanded digital signals in which items of said pixel datacorresponding to some of said pixels periodically selected are expandedinto pixel data having a data length n (where n is an integer equal toor larger than 2) times longer than said first data length; first andsecond branching means respectively supplied with said phase-expandeddigital signals, each of said first and second branching means branchinga route for the phase-expanded digital signal into a first route onwhich the polarity of the digital signal is not inverted and a secondroute on which the polarity of the digital signal is inverted bypolarity inversion means; first selection means for selecting one ofsaid first and second routes branched by said first branching means;second selection means for selecting one of said first and second routesbranched by said second branching means; and first and seconddigital-to-analog conversion means for respectively analog-to-digitalconverting the two phase-expanded digital signals selected by said firstand second selection means to output two first phase-expanded analogsignals, wherein said signal supply means supplies said pixel datasignals to said data signal lines on the basis of said two firstphase-expanded analog signals.
 7. An image display apparatus accordingto claim 6, further comprising:second phase expansion means for forming,from said two first phase-expanded analog signals, n X N (N: an integer)second phase-expanded analog signals expanded into pixel data byextending the data length of items of said pixel data corresponding tosome of said pixels periodically selected, said second phase expansionmeans outputting the second phase-expanded analog signals to n X Nphase-expanded signal output lines in parallel with each other, whereinsaid signal supply means supplies said pixel data signals to said datasignal lines on the basis of said n X N second phase-expanded analogsignals.
 8. An image display apparatus according to claim 7, whereinsaid signal supply means supplies said pixel data to said plurality ofdata signal lines on the basis of said n X N second phase-expandedanalog signals input through n X N signal supply lines, said imagedisplay apparatus further comprising:connection change means forchanging connections between said n X N phase-expanded signal outputline and said n X N signal supply lines; and change control means forcontrolling change of the order of phase expansion performed by each ofsaid first and second phase expansion means, and a combination ofconnections changed by said connection change means by linking thecombination to said phase expansion order.
 9. An image display apparatusaccording to claim 6, wherein a first-polarity gamma correction circuitand a first-polarity clamp circuit are connected in a stage subsequentto said first digital-to-analog conversion means, andwherein asecond-polarity gamma correction circuit and a second-polarity clampcircuit are connected in a stage subsequent to said seconddigital-to-analog conversion means.
 10. An image display apparatusaccording to claim 6, wherein said change control means controls saidfirst and second phase expansion means and said connection change meansby selecting at least one of predetermined n X N phase expansion ordersfor said first and second phase expansion means, and by also selectingone of a plurality of predetermined combinations of connections as thecombination of connections changed by said connection change means. 11.An image display apparatus according to claim 6, wherein said changecontrol means controls change of the order of phase expansion performedby said first and second phase expansion means and the combination ofconnections changed by said connection change means so that the voltagesapplied to said pixels differ in polarity one from another with respectto the pixels connected in common to each of said scanning signal lines.12. An image display apparatus according to claim 6, wherein said changecontrol means controls change of the order of phase expansion performedby said first and second phase expansion means and the combination ofconnections changed by said connection change means so that the voltagesapplied to said pixels are changed in polarity one from another insynchronization with a horizontal synchronization signal with respect tothe pixels connected in common to each of said data lines.
 13. An imagedisplay apparatus according to claim 6, wherein said change controlmeans controls change of the order of phase expansion performed by saidfirst and second phase expansion means and the combination ofconnections changed by said connection change means so that said datasampling section in which data of the leading pixel of one frame issampled is changed with respect to frames in synchronization with avertical synchronization signal.
 14. An image display apparatushaving:an image display unit in which pixels electrically connected to aplurality of data signal lines and to a plurality of scanning signallines are arrayed in a matrix form; scanning signal line selection meansfor supplying said scanning signal lines with scanning signals forsuccessively selecting said scanning signal lines; and signal supplymeans for supplying pixel data signals to said plurality of data signallines, said apparatus driving said pixels by applying voltages to thepixels in accordance with said data signals and said scanning signalswhile inverting the polarities of the voltages applied to the pixels,said apparatus comprising:first phase expansion means supplied with adigital signal having pixel data of a first data length corresponding tothe position of each of said pixels, said first phase expansion meansoutputting two phase-expanded digital signals in which items of saidpixel data corresponding to some of said pixels periodically selectedare expanded into pixel data having a data length n (where n is aninteger equal to or larger than 2) times longer than said first datalength; polarity determination means supplied with said twophase-expanded digital signals, said polarity determination meansdetermining the polarities of said two phase-expanded digital signals byleading one of said phase-expanded digital signals to a first route onwhich the polarity of the digital signal is not inverted and leading theother of said phase-expanded digital signals to a second route on whichthe polarity of the digital signal is inverted by polarity inversionmeans; first and second digital-to-analog conversion means forrespectively analog-to-digital converting said two phase-expandeddigital signals having the determined polarities to output two firstphase-expanded analog signals, wherein said signal supply means suppliessaid pixel data signals to said data signal lines on the basis of saidtwo first phase-expanded analog signals.